In recent years, high-speed IO interfaces, such as SD eXtended capacity (SDXC), universal serial bus (USB), and serial advanced technology attachment (SATA) have become increasingly fast. There has been proposed data transfer technology that achieves more efficient data transfer without compromising the high-speed throughput features of IO interfaces in executing a plurality of data transfers between a buffer in an IO interface and a main storage apparatus has also been proposed. For example, PTLs 1 and 2 propose direct memory access (DMA) transfer technology that uses descriptors.
For example, PTL 1 discloses a technique that allows, through DMA transfer that uses descriptors, detection of a data error during data transfer while also reducing the load on a host central processing unit (CPU). More specifically, upon detection of an error during data transfer, a DMA controller (DMAC: data transfer control apparatus) performs data transfer reusing the same DMA parameter as that which was used for transferring the data in which the error was detected. The parameter used for data transfer (hereinafter called “DMA parameter”) may include, for example, data transfer source address, transfer destination address, and transfer data size. In other words, the error data is overwritten by data transferred successfully using the same DMA parameter. This allows the data transfer control apparatus to discard the error data. Thus, the DMA transfer of PTL 1 achieves an increase in total throughput (more efficient data transfer) by discarding error data without any processing at the host CPU.
PTL 2 discloses making data transfer parallel by providing a queuing mechanism for DMA parameter settings and DMA activation requests, thus achieving more efficient data transfer.